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1997 microchip technology inc. ds21125c-page 1 features voltage operating range: 4.5v to 5.5v - maximum write current 3 ma at 5.5v - maximum read current 150 m a at 5.5v - standby current 1 m a typical 1 mhz se2.bus two wire protocol up to eight devices may be connected to the same bus for up to 512k bits total memory programmable block security options programmable endurance options schmitt trigger inputs for noise suppression self-timed erase and write cycles power on/off data protection circuitry endurance: - 10,000,000 e/w cycles guaranteed for a 4k block - 1,000,000 e/w cycles guaranteed for a 60k block variable page size up to 64 bytes 8 byte x 8 line input cache (64 bytes) for fast write loads <3 ms typical write cycle time, byte or page electrostatic discharge protection > 4000v data retention > 200 years 8-pin pdip/soic packages temperature ranges description the microchip technology inc. 24FC65 is a ?mart 8k 8x 8 serial electrically erasable prom (eeprom) with a high-speed 1mhz se2.bus whose protocol is functionally equivalent to the industry-standard i 2 c bus. this device has been developed for advanced applica- tions such as personal communications, and provides the systems designer with ?xibility through the use of many new user-programmable features. the 24FC65 offers a relocatable 4k-bit block of ultra-high-endurance memory for data that changes frequently. the remain- der of the array, or 60k bits, is rated at 1,000,000 erase/write (e/w) cycles guaranteed. the 24FC65 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. this device also features programmable security options for e/w protec- tion of critical data and/or code of up to ?teen 4k blocks. functional address lines allow the connection of - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c up to eight 24FC65's on the same bus for up to 512k bits contiguous eeprom memory. the 24FC65 is available in the standard 8-pin plastic dip and 8-pin surface mount soic package. 24FC65 64k 5.0v 1 mhz i 2 c smart serial eeprom package types block diagram 24FC65 a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc nc scl sda 24FC65 a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc nc scl sda pdip soic a0..a2 i/o control logic i/o sda scl vcc vss memory control logic xdec hv generator eeprom array page latches ydec cache sense amp r/w control i 2 c is a trademark of philips corporation. smart serial is a trademark of microchip technology inc.
24FC65 ds21125c -page 2 1997 microchip technology inc. 1.0 electrical chara cteristics 1.1 maxim um ratings* v cc ................................................................................... 7.0v all inputs and outputs w .r .t. v ss ................ -0.6v to v cc +1.0v stor age temper ature ..................................... -65 c to +150 c ambient temp . with po w er applied ................. -65 c to +125 c solder ing temper ature of leads (10 seconds) ............. +300 c esd protection on all pins .................................................. 3 4 kv *notice: stresses abo v e those listed under ?axim um ratings ma y cause per manent damage to the de vice . this is a stress r at- ing only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ational listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . t able 1-1: pin function tab le name function a0..a2 user con gur ab le chip selects v ss ground sda ser ial address/data i/o scl ser ial cloc k v cc +4.5v to 5.5v p o w er supply nc no internal connection t able 1-2: dc chara cteristics figure 1-1: bus timing star t/stop v cc = +4.5v to +5.5v commercial (c): t amb = 0 c to +70 c industr ial (i): t amb = -40 c to +85 c p arameter symbol min max units conditions a0, a1, a2, scl and sd a pins: high le v el input v oltage lo w le v el input v oltage hysteresis of scl and sd a lo w le v el output v oltage of sd a v ih v il v hys v ol 0.7 v cc 0.05 v cc 0.3 vcc 0.40 v v v v (note) i ol = 3.0 ma input leakage current i li -10 10 m a v in = 0.1v to v cc output leakage current i lo -10 10 m a v out = 0.1v to v cc pin capacitance (all inputs/outputs) c int 10 pf v cc = 5.0v (note) t amb = 25?c , f clk = 1 mhz oper ating current i cc w r ite i cc read 3 150 ma m a v cc = 5.5v, scl = 1 m h z v cc = 5.5v , scl = 1 mhz standb y current i ccs 5 m a v cc = 5.5v , scl = sd a =v cc a0, a1, a2, wp = v ss note 1: this par ameter is per iodically sampled and not 100% tested. scl sd a st ar t st op v hys t su : sto t hd : sta t su : sta
1997 microchip technology inc. ds21125c -page 3 24FC65 t able 1-3: ac characteristics figure 1-2: bus timing data p arameter symbol 1 mhz bus units remarks min max cloc k frequency f clk 0 1000 khz cloc k high time thigh 500 ns cloc k lo w time t low 500 ns sd a and scl r ise time t r 300 ns (note 1) sd a and scl f all time t f 10 0 ns (note 1) st ar t hold time t hd : sta 250 ns after this per iod the rst cloc k pulse is gener ated st ar t setup time t su : sta 250 ns only rele v ant f or repeated st ar t data input hold time t hd : dat 0 ns data input setup time t su : dat 100 ns st op setup time t su : sto 250 ns output v alid from cloc k t aa 350 ns (note 2) bus free time t buf 500 ns time the b us m ust be free bef ore a ne w tr ansmission can star t wr ite cycle time t wr 5 ms/page (note 3) endur ance high endur ance bloc k rest of arr a y 10m 1m cycles 25 c , vcc = 5.0v , bloc k mode ( note 4 ) note 1: not 100 percent tested. 2: as a tr ansmitter , the de vice m ust pro vide an inter nal minim um dela y time to br idge the unde ned region (min- im um 100 ns) of the f alling edge of scl to a v oid unintended gener ation of st ar t or st ops . 3: the times sho wn are f or a single page of 8 b ytes . multiply b y the n umber of pages loaded into the wr ite cache f or total time . 4: this par ameter is not tested b ut guar anteed b y char acter ization. f or endur ance estimates in a speci c appli- cation, please consult the t otal endur ance model which can be obtained on our bbs or w ebsite . scl sd a in sd a out t su : sta t sp t aa t f t low t high t hd : sta t hd : dat t su : dat t su : sto t buf t aa t r
24FC65 ds21125c -page 4 1997 microchip technology inc. 2.0 functional description the 24FC65 suppor ts a bidirectional tw o-wire b us and data tr ansmission protocol. a de vice that sends data onto the b us is de ned as tr ansmitter , and a de vice receiving data as receiv er . the b us m ust be controlled b y a master de vice which gener ates the ser ial cloc k (scl), controls the b us access , and gener ates the st ar t and st ops , while the 24FC65 w or ks as sla v e . both master and sla v e can oper ate as tr ansmitter or receiv er b ut the master de vice deter mines which mode is activ ated. 3.0 b us chara cteristics the f ollo wing b us pr otocol has been de ned: data tr ansf er ma y be initiated only when the b us is not b usy . dur ing data tr ansf er , the data line m ust remain stab le whene v er the cloc k line is high. changes in the data line while the cloc k line is high will be inter preted as a st ar t or st op . accordingly , the f ollo wing b us conditions ha v e been de ned ( figure 3-1 ). 3.1 bus not busy (a) both data and cloc k lines remain high. 3.2 star t data t ransf er (b) a high to lo w tr ansition of the sd a line while the cloc k (scl) is high deter mines a st ar t . all commands m ust be preceded b y a st ar t . 3.3 stop data t ransf er (c) a lo w to high tr ansition of the sd a line while the cloc k (scl) is high deter mines a st op . all oper ations m ust be ended with a st op . 3.4 data v alid (d) the state of the data line represents v alid data when, after a st ar t , the data line is stab le f or the dur ation of the high per iod of the cloc k signal. the data on the line m ust be changed dur ing the lo w per iod of the cloc k signal. there is one cloc k pulse per bit of data. each data tr ansf er is initiated with a st ar t and ter minated with a st op . the n umber of the data b ytes tr ansf erred betw een the st ar t and st ops is deter mined b y the master de vice . 3.5 ac kno wledg e each receiving de vice , when addressed, is ob liged to gener ate an ac kno wledge after the reception of each b yte . the master de vice m ust gener ate an e xtr a cloc k pulse which is associated with this ac kno wledge bit. a de vice that ac kno wledges m ust pull do wn the sd a line dur ing the ac kno wledge cloc k pulse in such a w a y that the sd a line is stab le lo w dur ing the high per iod of the ac kno wledge related cloc k pulse . of course , setup and hold times m ust be tak en into account. dur ing reads , a master m ust signal an end of data to the sla v e b y no t gener ating an ac kno wledge bit on the last b yte that has been cloc k ed out of the sla v e . in this case , the sla v e ( 24FC65 ) m ust lea v e the data line high to enab le the master to gener ate the st op . note: the 24FC65 does not gener ate an y ac kno wledge bits if an inter nal prog r am- ming cycle is in prog ress . figure 3-1: data t ransf er sequence on the serial bus scl sd a (a) (b) st ar t (c) (a) (d) (d) address or ac kno wledge v alid data allo w ed to change st op condition condition
1997 microchip technology inc. ds21125c -page 5 24FC65 3.6 de vice ad dressing a control b yte is the rst b yte receiv ed f ollo wing the st ar t from the master de vice . the control b yte consists of a f our bit control code , f or the 24FC65 this is set as 1010 binar y f or read and wr ite oper ations . the ne xt three bits of the control b yte are the de vice select bits (a2, a1, a0). the y are used b y the master de vice to select which of the eight de vices are to be accessed. these bits are in eff ect the three most signi cant bits of the w ord address . the last bit of the control b yte (r/ w ) de nes the oper ation to be perf or med. when set to a one a read oper ation is selected, when set to a z ero a wr ite oper a- tion is selected. the ne xt tw o b ytes receiv ed de ne the address of the rst data b yte ( figure 4-1 ). because only a12..a0 are used, the upper three address bits m ust be z eros . the most signi cant bit of the most signi cant b yte is tr ansf erred rst. f ollo wing the st ar t , the 24FC65 monitors the sd a b us chec king the de vice type identi er being tr ansmitted. upon receiving a 1010 code and appropr iate de vice select bits , the sla v e de vice ( 24FC65 ) outputs an ac kno wledge signal on the sd a line . depending upon the state of the r/ w bit, the 24FC65 will select a read or wr ite oper ation. figure 3-2: contr ol byte allocation operation contr ol code de vice select r/ w read 1010 de vice address 1 wr ite 1010 de vice address 0 sla ve address x = don? care 1 0 1 0 a2 a1 a0 r/w a st ar t read/ write 4.0 write opera tion 4.1 byte write f ollo wing the st ar t from the master , the control code (f our bits), the de vice select (three bits), and the r/ w bit which is a logic lo w is placed onto the b us b y the master tr ansmitter . this indicates to the addressed sla v e receiv er ( 24FC65 ) that a b yte with a w ord address will f ollo w after it has gener ated an ac kno wledge bit dur ing the ninth cloc k cycle . theref ore the ne xt b yte tr ansmitted b y the master is the high-order b yte of the w ord address and will be wr itten into the address pointer of the 24FC65 . the ne xt b yte is the least signi cant address b yte . after receiving another ac kno wledge signal from the 24FC65 the master de vice will tr ansmit the data w ord to be wr itten into the addressed memor y location. the 24FC65 ac kno wledges again and the master gener ates a st op . this initiates the inter nal wr ite cycle , and dur ing this time the 24FC65 will not gener ate ac kno wledge sig- nals ( figure 4-1 ). 4.2 p a g e write the wr ite control b yte , w ord address and the rst data b yte are tr ansmitted to the 24FC65 in the same w a y as in a b yte wr ite . but instead of gener ating a st op the master tr ansmits up to eight pages of eight data b ytes each (64 b ytes total) which are tempor ar ily stored in the on-chip page cache of the 24FC65 . the y will be wr itten from the cache into the eepr om arr a y after the master has tr ansmitted a st op . after the receipt of each w ord, the six lo w er order address pointer bits are inter nally incremented b y one . the higher order se v en bits of the w ord address remain constant. if the master should tr ansmit more than eight b ytes pr ior to gener ating the st op (wr iting across a page boundar y), the address counter (lo w er three bits) will roll o v er and the pointer will be incremented to point to the ne xt line in the cache . this can contin ue to occur up to eight times or until the cache is full, at which time a st op should be gener ated b y the master . if a st op is not receiv ed, the cache pointer will roll o v er to the rst line (b yte 0) of the cache , and an y fur ther data receiv ed will o v erwr ite pre viously captured data. the st op can be sent at an y time dur ing the tr ans- f er . as with the b yte wr ite oper ation, once the st op is receiv ed an inter nal wr ite cycle will begin. the 64 b yte cache will contin ue to capture data until a st op occurs or the oper ation is abor ted ( figure 4-2 ). figure 4-1: byte write b us a ctivity master sd a line b us a ctivity contr ol byte w ord address (1) a c k s t a r t w ord address (0) a c k a c k 0 s t o p a c k 0 0 d a t a
24FC65 ds21125c -page 6 1997 microchip technology inc. figure 4-2: p a g e write (for cac he write, see figure 7-1 ) figure 4-3: current ad dress read figure 4-4: rand o m read figure 4-5: seque n tial read b us master sd a line b us contr ol byte w ord address (1) s t o p s t a r t a c k 0 a c k a c k a ctivity : a ctivity : a c k a c k d a t a n d a t a n+7 0 0 w ord address (0) contr ol a c k s t a r t s t o p byte d a t a n b us a ctivity master sd a line b us a ctivity a c k n o b us master sd a line b us contr ol byte w ord address (1) s t o p s t a r t a c k a c k a c k a ctivity : a ctivity : a c k n o d a t a n 0 0 0 w ord address (0) s t a r t contr ol byte a c k a c k b us a ctivity master sd a line b us a ctivity contr ol byte d a t a n d a t a n+1 d a t a n+2 d a t a n+x a c k a c k a c k n o a c k s t o p
1997 microchip technology inc. ds21125c -page 7 24FC65 5.0 read opera tion read oper ations are initiated in the same w a y as wr ite oper ations with the e xception that the r/ w bit of the sla v e address is set to one . there are three basic types of read oper ations: current address read, r andom read, and sequential read. 5.1 current ad dress read the 24FC65 contains an address counter that maintains the address of the last w ord accessed, inter nally incremented b y one . theref ore , if the pre vious access (either a read or wr ite oper ation) w as to address n (n is an y legal address), the ne xt current address read oper ation w ould access data from address n + 1. upon receipt of the sla v e address with r/ w bit set to one , the 24FC65 issues an ac kno wledge and tr ansmits the eight bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a st op and the 24FC65 discontin ues tr ansmission ( figure 4-3 ). 5.2 random read random read oper ations allo w the master to access an y memor y location in a r andom manner . t o perf or m this type of read oper ation, rst the w ord address m ust be set. this is done b y sending the w ord address to the 24FC65 as par t of a wr ite oper ation (r/ w bit set to 0). after the w ord address is sent, the master gener ates a st ar t f ollo wing the ac kno wledge . this ter minates the wr ite oper ation, b ut not bef ore the inter nal address pointer is set. then the master issues the control b yte again b ut with the r/ w bit set to a one . the 24FC65 will then issue an ac kno wledge and tr ansmit the eight bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a st op which causes the 24FC65 to discontin ue tr ansmission ( figure 4-4 ). 5.3 sequential read sequential reads are initiated in the same w a y as a r andom read e xcept that after the 24FC65 tr ansmits the rst data b yte , the master issues an ac kno wledge as opposed to the st op used in a r andom read. this ac kno wledge directs the 24FC65 to tr ansmit the ne xt sequentially addressed 8 bit w ord ( figure 4-5 ). f ollo wing the nal b yte tr ansmitted to the master , the master will no t gener ate an ac kno wledge b ut will gener ate a st op . t o pro vide sequential reads the 24FC65 contains an inter nal address pointer which is incremented b y one at the completion of each oper ation. this address pointer allo ws the entire memor y contents to be ser ially read dur ing one oper ation. 5.4 contiguous ad dressing acr oss multiple de vices the de vice select bits a2, a1, a0 can be used to e xpand the contiguous address space f or up to 512k-bits b y adding up to eight 24FC65 's on the same b us . in this case , softw are can use a0 of the control b yte as address bit a13, a1 as address bit a14, and a2 as address bit a15. 5.5 noise pr otection the scl and sd a inputs incor por ate schmitt tr iggers which suppress noise spik es to assure proper de vice oper ation e v en on a noisy b us . 5.6 high endurance bloc k the location of the high-endur ance b loc k within the memor y map is prog r ammed b y setting the leading bit 7 (s/ he ) of the con gur ation b yte to 0. the upper bits of the address loaded in this command will deter mine which 4k b loc k within the memor y map will be set to high endur ance ( figure 8-1 ). this b loc k will be capab le of 10,000,000 er ase/wr ite cycles guar anteed. 5.7 security options the 24FC65 has a sophisticated mechanism f or wr ite-protecting por tions of the arr a y . this wr ite protect function is prog r ammab le and allo ws the user to protect 0-15 contiguous 4k b loc ks . the user sets the secur ity option b y sending to the de vice the star ting b loc k n um- ber f or the protected region and the n umber of b loc ks to be protected. if the secur ity option is in v ok ed with 0 b loc ks protected, then all por tions of the arr a y will be unprotected. all par ts will come from the f actor y in the def ault con gur ation with the star ting b loc k n umber set to 15 and the n umber of protected b loc ks set to z ero . the security option can be set onl y once. t o in v ok e the secur ity option, a wr ite command is sent to the de vice with the leading bit (bit7) of the rst address b yte set to a 1 ( figure 8-1 ). bits 1-4 of the rst address b yte de ne the star ting b loc k n umber f or the protected region. f or e xample , if the star ting b loc k n umber is to be set to 5, the rst address b yte w ould be 1xx0101x. bits 0, 5 and 6 of the rst address b yte are disregarded b y the de vice and can be either high or lo w . the de vice will ac kno wledge after the rst address b yte . a b yte of don't care bits is then sent b y the master , with the de vice ac kno wledging afterw ards . the third b yte sent to the de vice has bit7 (s/ he ) set high and bit6 (r) set lo w . bits 4 and 5 are don't cares and bits 0-3 de ne the n umber of b loc ks to be wr ite protected. f or e xample , if three b loc ks are to be protected, the third note: the high endur ance bloc k cannot be changed after the secur ity option has been set. if the h.e. b loc k is not prog r ammed b y the user , the def ault location is the highest b loc k of memor y .
24FC65 ds21125c -page 8 1997 microchip technology inc. b yte w ould be 10xx0011. after the third b yte is sent to the de vice , it will ac kno wledge and a st op bit is then sent b y the master to complete the command. dur ing a nor mal wr ite sequence , if an attempt is made to wr ite to a protected address , no data will be wr itten and the de vice will not repor t an error or abor t the command. if a wr ite command is attempted across a secure boundar y , unprotected addresses will be wr itten and protected addresses will not. 5.8 security con guration read the status of the secure por tion of memor y can be read b y using the same technique as prog r amming this option e xcept the read bit (bit 6) of the con gur ation b yte is set to a one . after the con gur ation b yte is sent, the de vice will ac kno wledge and then send tw o b ytes of data to the master just as in a nor mal read sequence . the master m ust ac kno wledge the rst b yte and not ac kno wledge the second, and then send a stop bit to end the sequence . the upper f our bits of both of these b ytes will alw a ys be read as '1's . the lo w er f our bits of the rst b yte contains the star ting secure b loc k. the lo w er f our bits of the second b yte contains the n umber of secure b loc ks . the def ault star ting secure b loc k is fteen and the def ault n umber of secure b loc ks is z ero ( figure 8-1 ). 6.0 a ckno wledge polling since the de vice will not ac kno wledge dur ing a wr ite cycle , this can be used to deter mine when the cycle is complete (this f eature can be used to maximiz e b us throughput). once the st op f or a wr ite command has been issued from the master , the de vice initiates the inter nally timed wr ite cycle . a ck polling can be initiated immediately . this in v olv es the master sending a st ar t f ollo w ed b y the control b yte f or a wr ite command (r/ w = 0). if the de vice is still b usy with the wr ite cycle , then no a ck will be retur ned. if the cycle is complete , then the de vice will retur n the a ck and the master can then proceed with the ne xt read or wr ite command. see figure 6-1 f or o w diag r am. figure 6-1: ac kno wledg e p olling flo w did de vice ac kno wledge (a ck = 0)? send wr ite command send stop condition to initiate wr ite cycle send star t send control byte with r/w = 0 ne xt oper ation no y es
1997 microchip technology inc. ds21125c -page 9 24FC65 7.0 p a ge ca che and arra y mapping the cache is a 64 b yte (8 pages x 8 b ytes) fifo b uff er . the cache allo ws the loading of up to 64 b ytes of data bef ore the wr ite cycle is actually begun, eff ectiv ely pro viding a 64-b yte b urst wr ite at the maxim um b us r ate . whene v er a wr ite command is initiated, the cache star ts loading and will contin ue to load until a stop bit is receiv ed to star t the inter nal wr ite cycle . the total length of the wr ite cycle will depend on ho w man y pages are loaded into the cache bef ore the stop bit is giv en. max- im um cycle time f or each page is 5 ms . ev en if a page is only par tially loaded, it will still require the same cycle time as a full page . if more than 64 b ytes of data are loaded bef ore the stop bit is giv en, the address pointer will wr ap around' to the beginning of cache page 0 and e xisting b ytes in the cache will be o v erwr itten. the de vice will not respond to an y commands while the wr ite cycle is in prog ress . 7.1 cac he write star ting at a p a g e boundar y if a wr ite command begins at a page boundar y (address bits a2, a1 and a0 are z ero), then all data loaded into the cache will be wr itten to the arr a y in sequential addresses . this includes wr iting across a 4k b loc k boundar y . in the e xample sho wn belo w , ( figure 7-1 ) a wr ite command is initiated star ting at b yte 0 of page 3 with a fully loaded cache (64 b ytes). the rst b yte in the cache is wr itten to b yte 0 of page 3 (of the arr a y), with the remaining pages in the cache wr itten to sequential pages in the arr a y . a wr ite cycle is e x ecuted after each page is wr itten. since the wr ite begins at page 3 and 8 pages are loaded into the cache , the last 3 pages of the cache are wr itten to the ne xt ro w in the arr a y . 7.2 cac he write star ting at a non-p a g e boundar y when a wr ite command is initiated that does not begin at a page boundar y (i.e ., address bits a2, a1 and a0 are not all z ero), it is impor tant to note ho w the data is loaded into the cache , and ho w the data in the cache is wr itten to the arr a y . when a wr ite command begins , the rst b yte loaded into the cache is alw a ys loaded into page 0. the b yte within page 0 of the cache where the load begins is deter mined b y the three least signi cant address bits (a2, a1, a0) that w ere sent as par t of the wr ite command. if the wr ite command does not star t at b yte 0 of a page and the cache is fully loaded, then the last b yte(s) loaded into the cache will roll around to page 0 of the cache and ll the remaining empty b ytes . if more than 64 b ytes of data are loaded into the cache , data already loaded will be o v erwr itten. in the e xample sho wn in figure 7-2 , a wr ite command has been initiated star ting at b yte 2 of page 3 in the arr a y with a fully loaded cache of 64 b ytes . since the cache star ted loading at b yte 2, the last tw o b ytes loaded into the cache will roll o v er' and be loaded into the rst tw o b ytes of page 0 (of the cache). when the stop bit is sent, page 0 of the cache is wr itten to page 3 of the arr a y . the remaining pages in the cache are then loaded sequentially to the arr a y . a wr ite cycle is e x ecuted after each page is wr itten. if a par tially loaded page in the cache remains when the st op bit is sent, only the b ytes that ha v e been loaded will be wr itten to the arr a y . 7.3 p o wer mana g ement the design incor por ates a po w er standb y mode when not in use and automatically po w ers off after the nor mal ter mination of an y oper ation when a stop bit is receiv ed and all inter nal functions are complete . this includes an y error conditions , i.e . not receiving an ac kno wledge or st op per the tw o-wire b us speci cation. the de vice also incor por ates v dd monitor circuitr y to pre v ent inad- v er tent wr ites (data corr uption) dur ing lo w-v oltage con- ditions . the v dd monitor circuitr y is po w ered off when the de vice is in standb y mode in order to fur ther reduce po w er consumption.
24FC65 ds21125c -page 10 1997 microchip technology inc. figure 7-1: cac he write to the arra y star ting at a p a g e boundar y figure 7-2: cac he write to the arra y star ting at a non-p a g e boundar y 1 wr ite command initiated at b yte 0 of page 3 in the arr a y; first data b yte is loaded into the cache b yte 0. 2 64 b ytes of data are loaded into cache . cache page 0 cache b yte 0 cache b yte 1 cache b yte 7 cache page 1 b ytes 8-15 cache page 2 b ytes 16-23 cache page 7 b ytes 56-63 4 remaining pages in cache are wr itten to sequential pages in arr a y . page 0 page 1 page 2 b yte 0 b yte 1 b yte 7 page 4 page 0 page 1 page 2 page 3 page 4 page 7 page 7 arr a y ro w n arr a y ro w n + 1 3 wr ite from cache into arr a y initiated b y st op bit. p age 0 of cache wr itten to page 3 of arr a y . wr ite cycle is e x ecuted after e v er y page is wr itten. 5 last page in cache wr itten to page 2 in ne xt ro w . 1 wr ite command initiated; 64 b ytes of data loaded into cache star ting at b yte 2 of page 0. cache b yte 0 cache b yte 1 cache b yte 7 cache page 1 b ytes 8-15 cache page 2 b ytes 16-23 cache page 7 b ytes 56-63 page 0 page 1 page 2 b yte 0 b yte 1 page 4 page 0 page 1 page 2 page 3 page 4 page 7 page 7 4 wr ite from cache into arr a y initiated b y st op bit. p age 0 of cache wr itten to page 3 of arr a y . wr ite cycle is e x ecuted after e v er y page is wr itten. 6 last 3 pages in cache wr itten to ne xt ro w in arr a y . cache b yte 2 2 last 2 b ytes ?oll e v er to beginning. 3 5 remaining b ytes in cache are wr itten sequentially to arr a y . last 2 b ytes loaded into page 0 of cache . b yte 2 b yte 3 b yte 4 b yte 7 arr a y ro w n arr a y ro w n+1
1997 microchip technology inc. ds21125c -page 11 24FC65 8.0 pin descriptions 8.1 a0, a1, a2 chip ad dress inputs the a0..a2 inputs are used b y the 24FC65 f or m ultiple de vice oper ation and conf or m to the tw o-wire b us standard. the le v els applied to these pins de ne the address b loc k occupied b y the de vice in the address map . a par ticular de vice is selected b y tr ansmitting the corresponding bits (a2, a1, a0) in the control b yte ( figure 3-2 and figure 8-1 ). 8.2 sd a serial ad dress/data input/output this is a bidirectional pin used to tr ansf er addresses and data into and data out of the de vice . it is an open dr ain ter minal, theref ore the sd a b us requires a pullup resistor to v cc (typical 1k w, m ust consider total b us capacitance and maxim um r ise/f all times). f or nor mal data tr ansf er sd a is allo w ed to change only dur ing scl lo w . changes dur ing scl high are reser v ed f or indicating the st ar t and st ops . 8.3 scl serial cloc k this input is used to synchroniz e the data tr ansf er from and to the de vice . figure 8-1: contr ol sequence bit assignments r x x b 3 b 2 b 1 b 0 s 0 0 a 12 a 11 a 10 a 9 a 8 contr ol byte address byte 0 1 0 1 0 a 2 a 1 a 0 r w a 7 a 0 address byte 1 configura tion byte sla v e address de vice select bits bloc k count s/he ac kno wledges from de vice s s a data from de vice 1 0 1 0 a 2 a 1 a 0 0 c k a c k a c k a c k 1 x x x x x x x x x x x x x x x 1 1 x x x x x x 1 1 1 1 b 3 b 2 b 1 b 0 a c k 1 1 1 1 n 3 n 2 n 1 n 0 data from de vice s/he star ting bloc k number number of bloc ks to protect no a ck t o p ac kno wledge from master t a r t security read r ac kno wledges from de vice s s a 1 0 1 0 a 2 a 1 a 0 0 c k a c k a c k a c k 1 x x x x x x x x x x x 1 0 x x n 3 n 2 n 1 n 0 s/he t o p t a r t security write b 3 b 2 b 1 b 0 r star ting bloc k number number of bloc ks to protect ac kno wledges from de vice s s a data from de vice 1 0 1 0 a 2 a 1 a 0 0 c k a c k a c k a c k 1 x x x x x x x x x x x x x x x 0 1 x x x x x x 1 1 1 1 b 3 b 2 b 1 b 0 a c k high endur ance bloc k number no a ck t o p t a r t high endurance bloc k read r s/he ac kno wledges from de vice s s a 1 0 1 0 a 2 a 1 a 0 0 c k a c k a c k a c k 1 x x x x x x x x x x x 0 0 x x 0 0 0 0 b 3 b 2 b 1 b 0 s/he t o p t a r t high endurance bloc k write r high endur ance bloc k number
24FC65 ds21125c -page 12 1997 microchip technology inc. notes:
1997 microchip technology inc. ds21125c -page 13 24FC65 notes:
24FC65 ds21125c -page 14 1997 microchip technology inc. notes:
24FC65 1997 microchip technology inc. ds21125c -page 15 24FC65 pr oduct identi cation system t o order or to obtain inf or mation (e .g., on pr icing or deliv er y), please use the listed par t n umbers , and ref er to the f actor y or the listed sales of ces . p ac ka g e: p = plastic dip (300 mil body) sm = plastic soic (207 mil body , eiaj standard) t emperature blank = 0 c to +70 c rang e: i = -40 c to +85 c de vice: 24FC65 64k, 1mhz i 2 c ser ial eepr om 24FC65t 64k, 1mhz i 2 c ser ial eepr om (t ape & reel) 24FC65 /p
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